The evolution from wireless based voice only communication networks to wireless based voice and data communication networks has resulted in the development of global system for mobile communications (GSM) and general packet radio service (GPRS) into the enhanced data for global evolution (EDGE) standard. Although speech still remains the dominant service by many cellular service providers, existing systems are being upgraded to provide greater support for data communication via the radio interface.
The GSM standard, for example, provides data services with bit rates up to 14.4 kbps for circuit-switched data and up to 22.8 kbps for packet based (non-circuit switched) data. For GSM, higher bit rates may be achieved utilizing technological advancements such as high-speed circuit-switched data (HSCSD) technology and general packet radio service (GPRS) technology, which are based on the original gaussian minimum shift keying (GMSK) modulation scheme employed by GSM.
Enhanced data for global evolution (EDGE) is an enhancement to GPRS that leverages a new modulation scheme along with various coding and radio link enhancements to provide much higher bit rates and capacity. Due to the higher bit rate and the need to adapt the data protection to the channel and link quality, the EDGE radio link control (RLC) protocol is somewhat different from the corresponding GPRS protocol. Various link quality control (QC) techniques are utilized for adapting the robustness of a radio link to varying channel quality. Link adaptation (LA) and incremental redundancy (IR) are two quality control techniques that may be utilized to adapt the robustness of a radio link to varying channel quality. The link adaptation technique periodically generates estimates of the link quality and accordingly selects an appropriate modulation and coding scheme for handling transmissions over that communication link so as to maximize the corresponding bit error rate.
EDGE utilizes the incremental redundancy quality control technique to adapt the robustness of a radio link to varying channel quality. With incremental redundancy (IR), information may originally be transmitted utilizing as little coding as possible so as to achieve the highest possible bit rate for the link if decoding is immediately successful. However, in instances where this minimal coding results in a failure during the corresponding decoding process, then more coding is added, thereby increasing the redundancy, until the corresponding decoding process succeeds. In this regard, the additional redundant bits increase the amount of bits that have to be sent, thereby decreasing the bit rate and increasing latency.
FIG. 1 is a block diagram of a conventional message processor implementation 102 that is utilized for GSM, GPRS or EDGE systems. Referring to FIG. 1, there is shown a message processing system 102, which comprises core processor block 104, memory block 106, a DSP block 108, and register block 112. The DSP block 108 may comprise a message processor block (MP) 110 and a message processor memory block 114. The conventional message processor implementation 102 of FIG. 1 may be part of a GSM, GPRS or EDGE handset.
The core processor block 104 may be, for example, a conventional ARM processor. The memory block 106 may be adapted to store and transfer data to the message processor memory 114. The DSP 108 may be adapted to handle transfer of large quantities of data from the message processor memory 114 to the memory block 106. The register block 112 may comprise a plurality of registers for facilitating transfer of data and memory handling functions. The message processor block (MP) 110 may be utilized to implement various channel encoding and decoding functions, which on a conventional processing system as illustrated in FIG. 1, resides in a DSP subsystem such as DSP 108.
The message processor 110 may be adapted to receive information from a transceiver and decode the received information. The message processor memory 114 may be adapted to store large quantities of data that may be transferred from the memory block 106. During data transmission, the message processor 110 may be adapted to code information to be transmitted using a particular coding algorithm. For incremental redundancy, the message processor 110 may be adapted to incrementally code additional bits of information to mitigate the effects of impairments in a communication link.
The incremental redundancy (IR) function utilized by EDGE requires an extensive amount of processing power and bandwidth. For example, the DSP 108 must handle the transfer of large quantities of data from the message processor memory 114 to the memory block 106. Similarly, the core processor 104 must also handle the transfer of large quantities of data from the memory block 106 to the message processor memory 114. These transfers consume a large portion of the processing bandwidth of the core processor 104 and the DSP 108. Accordingly, the incremental redundancy (IR) function utilized by EDGE makes implementing the message processing function in the DSP 108 an inefficient solution.
In conventional systems, when data is to be transmitted, it must be placed in the message processor 110 by DSP 108. The message processor 110 may then code the data for transmission. After coding, the resulting coded data may be placed in a transmit (Tx) buffer from which it is retrieved for transmission. On the receive side, the received data may be acquired from a receive (Rx) buffer by the message processor 110. The data acquired from the receive buffer may then be decoded by the message processor and transferred to the memory 106 by the DSP 108. The ARM 104 may then acquire the decoded data from the memory 106.
For EDGE, IR allows some or all data to be transmitted when errors occur. IR allows variation of coded data to be retransmitted to compensate or correct data in error. When these variations of coded data are received, the DSP may decode any combination of the previously received data and current variations of the coded data. This requires the previously received data to be stored in the DSP memory. However, the DSP memory is very small and the amount of data that may be stored there is limited. To solve this problem, since the memory 106 may be quite large, the data required for IR may be stored in the memory 106. The ARM processor 104 may therefore combine the previously received data with the current variations of data and store the resulting data back in the memory 106. This combined data may then be acquired by the DSP 108 from the memory 106. All this transfer of data requires a lot of processing cycles, which increases system latency and reduces system performance.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.